A Coarse-Fine Dual Loop Digital Low Dropout Regulator with Fast Transient Response

A coarse-fine dual loop digital LDO with fast transient response is proposed in this paper. The proposed digital LDO incorporates both undershoot detector and gate-bulk dual modulation technology to reduce the output voltage' undershoot. In order to improve process scalability, the controller of the digital LDO only employs digital standard cells, in which the dynamic comparator is replaced by a synthesizable digital comparator. The digital LDO is simulated in a 65nm CMOS process. A 0.5V stable output voltage and a 20mA output current is achieved with a 0.6V input voltage. A maximum voltage undershoot of 90mv is simulated with a 15mA load step and a total capacitor of 130pF.