A Low Power Up/Down Double-Data-Rate Counter for CMOS Image Sensors

A novel low power column level up/down double data-rate (DDR) counter for CMOS image sensors is proposed. To reduce the power consumption, a lowest bit circuit recording the parity information of the signal is designed. The proposed counter is suitable for the digital correlated double sampling operation. A 11-bit counter is realized with a 65nm CMOS process and the total power consumption in 500MHz clock is only 5.68 which is 80.6% compared to a traditional up/down DDR counter.