An Efficient Real-Time Two-Dimensional CA-CFAR Hardware Engine

In this paper, an FPGA-based implementation of two-dimensional cell average constant false alarm rate (CACFAR) hardware engine applied in range-doppler map (RDM) is presented. A lot of operations are reduced by avoiding repeated calculations. Data can be handled in real time through pipeline. The implementation results with an xc7a100tcsg324-1 FPGA device are that 2816 look-up tables (LUTs) are used in the design and the throughput is 114.19 million cells per second.