Design and Implementation of CMOS Full Adder Circuit with ECRL and Sleepy Keeper Technique

In this paper ECRL with sleepy keeper technique have been presented. The proposed adder shows less power dissipation and less power delay product (PDP). The circuits have been simulated in 0.18μm CMOS technology using Mentor Graphics. The proposed Full adder indicates power dissipation of 129.819pW with a delay of 135.97ns at supply voltage of 1.8V. Simulations have been completed with different supply voltages [1.0 – 1.8] V. Power dissipation of proposed full adder circuit have been contrasted with earlier reported full adder designed circuits and proposed approach indicates better outcomes.