A High Precision Low Distortion Current Squarer/Divider Circuit Based on FGMOS Translinear Principle

A high linear high speed low distortion current squarer/divider circuit is proposed in this paper. The presented circuit is based on floating-gate MOS translinear (FGMTL) principle in saturation region and consists of a dual translinear loop. The designed circuit is simulated by HSPICE simulator in TSMC 0.18 μm (level-49 parameters) CMOS technology. Simulation results of the current squarer circuit with 1-V DC supply voltage show that the maximum nonlinearity as 0.75%, the -3dB bandwidth as 1.15 GHz, the total harmonic distortion (THD) as 0.25% (at 1 MHz), the maximum and static power consumption are 82 μW and 20.5 μW, respectively. Monte Carlo simulations are also performed that prove their superiority over some other art works and robustness against PVT (process, voltage and temperature) variations.