Bringing 3D COTS DRAM Memory Cubes to Space

This paper details the architectural choices and implementation challenges faced in the building and validation of a space-qualified 3D DRAM memory system, in an effort to offer high memory capacity, increased bandwidth, fault tolerance and improved size-weight-and-power characteristics needed for harsh space mission environments. Our novel horizontal 3D stacking technology called “Loaf-Of-Bread” (LOB) is used to integrate multiple Commercial-Off-The-Shelf (COTS) DRAM memory dies into a cube structure (3D-M
³
). A custom Radiation-Hardened-By-Design (RHBD) controller sitting underneath the cube supplements the 3D-M
³
in addressing COTS radiation weaknesses by including advanced SEU and SEFI mitigation features such as error detection and correction, scrubbing, device data rebuilding and die management. We developed a custom DDR physical layer (PHY) for 14 independent dies to connect the 3D-M
³
to its controller. Validation and functional evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack. The selected test methodology ensures high-quality RTL as well as allows to subject the cube structure to radiation testing. The proposed design concept allows for flexibility in the choice of the DRAM die in case of technology roadmap changes or unsatisfactory radiation results.