Robust ESD Implanted 5V GGNMOS Clamp Design and Process optimization with maximized ESD Design Window

Design and process optimization of an ESD implanted 5V GGNMOS clamp for high ESD robustness and maximized ESD design window was investigated. Design optimization of the shape and location of the ESD implant (especially, Poly-to-ESD spacing, SPC) together with process co-optimization (ESD implant dose) could maximize the ESD design window while balancing DC Leakage. A comparative analysis between two distinct clamp designs is presented.