Neural Network-Based 3D IC Interconnect Capacitance Extraction

This paper presents a method to extract interconnect capacitance in three-dimensional integrated circuits (3D ICs) using a neural network (NN). The procedure is as follows: (1) create training datasets (by obtaining capacitance values from the complicated 3D interconnect structures using a 3D electromagnetic field solver), (2) build the trained models by inputting the training datasets to the NN, and (3) extract capacitance values by inputting structural parameters regarding the objective interconnect. The structures of general interconnects, interconnects surrounding a through-silicon via (TSV), and whole interconnects are examined. Experimental results show that the proposed NN-based extraction method can obtain reasonable accuracy and processing time. They also show that good trained models are obtained even if training datasets that integrate two structures into one are input to the NN.