Two-Stage Multi-bit Flip-Flop Clustering with Useful Skew for Low Power

In the modern system-on-chip (SoC) design, high speed and low power are the two most important objectives. It is recognized that useful skew between registers can be utilized to increase the timing slack and multi-bit flip-flop (MBFF) can be utilized to save the clock power consumption. In this paper, we propose a two-stage design flow to perform the clustering of MBFF with useful skew to minimize the power consumption under timing constraints. In the first stage, we consider the use of conventional MBFF. In the second stage, we consider the use of loosely coupled MBFF (LC-MBFF). To our knowledge, our approach is the first work that combines clock skew scheduling, MBFF and LC-MBFF. Experiment result consistently show that our approach can greatly reduce the power consumption.