Hardware Architecture Design of the Deep-learning-based Machine Vision Chip

This paper describes the mainstream hardware architectures of the existing deep learning computing devices, and proposes a heterogeneous multi-core SoC hardware architecture which includes DPUs for power grid system. It can greatly reduce the memory variables required for the computation while fully accelerating the deep learning operation by using DPU, and it has the characteristics of low power consumption. The proposed architecture is suitable for deep learning machine vision chips used in the condition monitoring of local equipment in the power grid system.