I. Introduction
Advancement in VLSI technology has made it possible to integrate large number of transistors on a single chip, which has driven to an era of a System on Chip (SoC). Power density in processing units has been increasing rapidly over the past few years, and expected to increase further because of the scaling in CMOS technology features, barring the reduction in operating voltage. Network on Chip (NoC) structures have been proposed [1] as a viable solution to mitigate the problems involving inter-core communication, synchronization etc. Power reduction and energy efficiency are the key constraints in the design of upcoming multi-core NoC architectures, which often lead to Dark Silicon [2]. The dynamic frequency scaling (DFS) is a hardware feature that can in real-time adjust the clock frequency based on the computational requirement of the IP core [3] [4]. It is an effective technique for increasing the energy efficiency of a network by reducing the overall energy dissipation. The main idea is to provide the circuit just enough of processing speed that suffices the assigned task. An important issue in NoC based multi-core system is how to map the tasks of an application to the cores such that utilization of system resources is maximized known as application mapping, while minimizing the energy consumption [5]. The application and the NoC topology can be represented as Core-graph and Topology-graph, respectively [6]. Thermal-safety during testing is also a determining factor of performance of such mapping. High local temperature gradient may create vicious thermal cycle, acting as positive feedback to increase in leakage power, interconnect delay and lead to chip failure [7]. High instantaneous rise in temperature may lead to catastrophic failure. As Network-on-Chip (NoC) consists of different cores, each having its own power-profile, area, frequency of operation etc, it results in nonuniform heating of the chip. This may result in delay variation across the chip. This not only affects circuit performance but also decreases their reliability. This necessitates the application mapping to not only satisfy the communication requirements but also their temperature profiles. The research problems that have been addressed in this paper are dynamic frequency scaling of heterogeneous cores and thermal aware application mapping. There exists a gap in the existing literature, where proposed solutions are sub-optimal based on either DFS, thermal safe power or communication based application mapping. In this work, a set of heuristics and optimization techniques have been proposed to bridge the gap, to get a more centralized solution addressing these problems altogether. The proposed approach establishes a trade-off between thermal budget and application finish time of the solution, besides producing results much superior to those of the existing techniques, reported in the literature. The following is the major contributions of this work:
Thermal aware static mapping and dynamic frequency scaling to minimize application finish-time with constraints on thermal budget