Power-Delay-Product, Area and Threshold-Loss Analysis of CMOS Full Adder Circuits

This paper presents an analysis of popular 1-bit full adder circuits. The analysis metrics comprised of power, delay, power-delay-product, area, and threshold loss. As an important unit of various hardware computational blocks, the transistor-level design of the full adder circuit has been evolving for decades. In this comparative study, we focus on the highly cited designs of last two decades. We use Microwind/DSCH simulator to evaluate the performance metrics. This paper serves as a quick reference for the VLSI designers and researchers in selecting appropriate circuit for the computational block and further improvement, respectively.