Parallelism Analysis for a Multi-core Speech Recognition Architecture

In this work, we present an analysis of data parallelism for a multiple core chip. The aim of this work is to optimally utilize different levels of spatial parallelism as a strategy to reduce the energy consumption of the whole architecture. The core in the analysis implements a Gaussian Mixture Model for automatic speech recognition. In the first place, we analyze the optimal degree of parallelism at the micro-architecture level. In the second place, we analyze the parallelism at the multiple core level and perform an optimization that minimizes the energy-delay product of the whole system. All analysis are performed using simulation data from synthesis in a 55nm CMOS technology.