Modeling and optimization of Array Leakage in 3D NAND Flash Memory

In this paper, complicated array leakage current of three-dimensional (3D) vertical channel NAND flash memory has been investigated and optimized. Monte Carlo simulation results show the design of channel hole layout, process variation of channel hole critical dimension are identified to the leakage issue. Experiment results show that the optimized layout, the elliptical outer hole profile and more uniform channel hole critical dimension lead to a significant leakage improvement.