An Implementation Issue for 3L PWM Techniques for Parallel Interleaved 2L VSIs

Different three-level (3L) pulse-width modulation (PWM) techniques could be implemented using two parallel interleaved two-level (2L) three phase voltage source inverters (VSIs). In case of two parallel interleaved 2L VSIs, there is a physical addition of voltage waveforms of individual 2L VSIs for constructing an equivalent 3L output voltage waveform. However, due to practical constraints such as dead-band, mismatch in device switching characteristics, delay due to logic gates, etc. there occurs an unwanted shift in the switching patterns which produces an unwanted variation in the equivalent 3L output voltage waveform. This unwanted variation in the equivalent 3L output voltage waveforms reflects as higher ripple in the ac side line currents of the individual VSIs and load current. This paper proposes a reference signal shifting based solution for mitigating the unwanted variation in the equivalent 3L output voltage waveform and hence reducing the ripple in the ac side currents. Simulation and experimental results are shown to validate the proposed method.