Synthesizing IEC 61499 Function Blocks to hardware

IEC 61499 Function Blocks is the emerging standard for distributed control of industrial automation systems. Within this domain, it is common for devices to need robust timing and functional guarantees. Unfortunately, many industry-standard approaches can only provide analysis for functional correctness. This is primarily because IEC 61499 is usually executed upon architectures and systems that are not amenable to static timing analysis, such as those that utilize general purpose processors or embedded operating systems. Hence, designers must rely on timing values obtained by measurement-based approaches, a methodology that will not be able to provide strong timing guarantees. In this paper, we propose a novel methodology for instead compiling Function Blocks to FPGA-based hardware, using synchronous semantics for their execution. To avoid restricting the functionality of these implementations, complex mechanisms such as software updates and distributed networking can be provided via on- or off-chip coprocessing. This overall approach provides for straightforward timing analysis, as well as a methodology for designing reliable, efficient controllers with extremely fast response times.