A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits

The rapid increase in complexity of digital VLSI circuits with the advent of Deep Sub-Micron (DSM) technology causes development of faults during their normal operation. Some non-modeled faults may not always be detectable by off-line test or Built-In-Self-Test (BIST), or a number of critical faults may require detection or alerts at the functional mode during run-time. On-line Testing (OLT) provides a solution to both problems, and can be implemented using appropriate Design-for-Testability (DFT) techniques. There are few OLT techniques for asynchronous circuits have been proposed as compared to synchronous circuits. The existing OLT techniques for asynchronous circuits have the issues of protocol dependency, high area overhead and scalability. In this work, we have proposed a partial replication based OLT technique for asynchronous circuits using Binary Decision Diagram (BDD). The proposed scheme works for all circuits irrespective of their design protocols and achieves comparatively low area overhead. Further, use of BDD enables the scheme to handle fairly large circuits.

I. Introduction

The complexity of digital VLSI circuits in recent years has increased in a very impressive manner. The sophistication of VLSI technology has reached a point where an effort is made to put a large number of devices on a single chip by decreasing the dimensions of the transistors and interconnection wires, from micrometers to nanometers. As the fabrication technology moves to lower sub-micron processes and engineers keep increasing the design complexity, testing encounters greater challenges [9]. Testing of digital VLSI circuits can be classified into two important classes; Offline testing and On-line Testing (OLT). The off-line testing strategies (Automatic Test Equipment (ATE)based testing and Built-In-Self-Test (BIST)[4], [11])cannot detect faults that develop on-the-fly during operation of the circuit. It has been observed that the probability of occurrence of such faults in the present day VLSI circuits designed using deep sub-micron technology is high [14], [21]. Therefore, OLT is becoming an indispensable part of testing. OLT can be defined as the procedure to enable integrated circuits to verify the correctness of their functionality during normal operation by checking whether the response of the circuit conforms to its desired dynamic behavior. In OLT, it requires an on-chip Design For Testability (DFT)circuity to test the CUT for all the input patterns that would appear during normal operation [7], [18], [22].