Non-Ideal Effects of Memristor-CMOS Hybrid Circuits for Realizing Multiple-Layer Neural Networks

In this paper, we analyze and discuss various non-ideal effects of Memristor-CMOS hybrid circuits to realize multiple-layer neural networks. The neural networks are composed of synapses and neurons. For mimicking synapses, memristors have been studied intensively many years as a potential candidate of hardware realization. The 3-dimensional connectivity in memristor crossbars seems very similar to the real neuronal structure in human's brain. In addition, memristor crossbars can calculate the weighted summation in parallel. This is very useful in performing Vector-Matrix Multiplication in crossbars like brain's parallel computation. For non-ideal effects, memristor crossbars can be susceptible to various variations in synaptic memristance, parasitic resistance, etc. We analyze and discuss these variations in memristor crossbars, in this paper, in terms of neural network's performance. For completing the neural networks, not only synapses but also neurons should be implemented. To do so, we consider the non-ideal effects of two CMOS neuron circuits which perform ReLU and Sigmoid activation functions, respectively. Because the circuit elements of CMOS neurons can also be susceptible to various Process-Voltage-Temperature variations, we analyze and discuss these effects. And, we combine all the non-ideal effects in Memristor-CMOS hybrid circuits and analyze how they affect the network's performance. These analysis results and discussion can be useful in combining the well-established CMOS technology with the new emerging devices such as memristors for realizing large-scale neural networks, to exploit various advantages of brain's architecture and function.