A Wideband High PSRR Capacitor-Less LDO with Adaptive DC Level Shift and Bulk-Driven Feed-Forward Techniques in 28nm CMOS

An analog solution of the capacitor-less low dropout regulator (CL-LDO) using the adaptive DC level shift (ADLS) and bulk-driven feed-forward (BDFF) techniques is proposed. The ADLS circuit is adopted to increase the headroom of the pass transistor's gate voltage, which achieves a larger current loading capability without increasing the size of the pass transistor. The BDFF technique decreases the threshold voltage of the pass transistor to improve its current driving capability and expand the bandwidth of the power supply rejection ratio (PSRR) by adding a feed-forward path at the pass transistor's bulk. The proposed LDO has been implemented in TSMC 28nm CMOS. The simulation results show that the proposed CL-LDO consumes 308 μA current from a 1.2-2.5V power supply, with a 0.7 to 0.9V output range. With 2pF internal capacitance, it can support 0-50mA load current within 80pF load capacitance range. The PSRR is under -20dB across 5MHz frequency range.