Design of Energy Efficient SRAM Cell Based on Double Gate Schottky-Barrier-Type GNRFET with Minimum Dimer Lines

The Static Random Access Memory (SRAM) consumes a significant amount of energy in any digital design. Therefore, it is necessary to design an energy efficient SRAM cell to improve overall energy consumption of the system. This paper evaluates the energy efficiency of double gate SB-GNRFET based 6T SRAM cell and compare to 10nm FinFET based 6T SRAM cell. It is observed that the double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume slightly more energy than FinFET based SRAM. It is also observed that GNRFET based SRAM is more stable and reliable than FinFET based SRAM. The paper also presents stability analysis of GNRFET based SRAM circuit under process variation to determine the robustness.