A Resource-Optimized VLSI Architecture for Patient-Specific Seizure Detection using Frontal-Lobe EEG

Design, VLSI implementation, and experimental validation of a resource-optimized machine-learning algorithm for epilepsy seizure detection is presented. The algorithm uses only signals from the frontal and the front-temporal lobes EEG electrodes while yielding a seizure detection performance competitive to the standard full EEG systems. The experimental validations prove the possibility of conducting accurate seizure detection using quickly-mountable dry-electrode headsets without the need for uncomfortable/painful through-hair electrodes or adhesive material. The compact VLSI implementation of the algorithm is also presented and resource optimization techniques are discussed. The optimized implementation is uploaded on an Actel Igloo AGL250 low-power FPGA, requires 1237 logic elements, consumes 110μW dynamic power, and yields a detection latency of 10.2μs. The measurement results from the FPGA implementation on data from 23 patients (198 seizures in total) shows a seizure detection sensitivity and specificity of 92.5% and 80.1%, respectively.