Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs

Modern transistors such as FinFETs and gate-all-around FETs (GAAFETs) suffer from excessive heat confinement due to their small size and three-dimensional geometries, with limited paths to the thermal ambient. This results in device self-heating, which can reduce speed, increase leakage, and accelerate aging. This paper characterizes the temperature for both the 7nm FinFET and 5nm GAAFET sub-structures and analyzes its impact on circuit performance (delay and power) and reliability (bias temperature instability, hot carrier injection, and electromigration). On average, logic gates in a circuit heat up by 12K for 7nm SOI FinFET and by 17K for 5nm GAAFET designs. This rise in temperature accelerates delay degradation due to bias temperature instability and hot carrier injection by up to 25% in FinFET and 39% in GAAFET designs, and also degrades the electromigration-induced time to failure of wires by up to 38% in SOI FinFET and 45% in GAAFET technologies.

I. Introduction

Traditional planar MOS devices at the 28nm node and higher have been built as (i) bulk MOSFETs on bulk Si wafers, or (ii) silicon-on-insulator (SOI) MOSFETs built above an insulating buried oxide (BOX) layer that improves performance by reducing leakage and parasitics. To enable efficient scaling, designs at the 16/14nm node are based on multigate 3D FinFETs that provide improved electrostatic control over the channel. These device topologies help reduce short channel effects, increase the drive current, enable the use of lower supply voltages, and provide superior scalability. These structures may also be constructed as bulk FinFETs on a bulk substrate, or SOI FinFETs, built above a BOX layer. The SOI FinFET provides similar advantages over the bulk FinFET as the SOI MOSFET over its bulk counterpart. Transistors continue to evolve to further enhance the gate surface area, while shrinking the device footprint. While the FinFET covers three surfaces of the fin, the gate-all-around FET (GAAFET) completely surrounds the channel. Lateral GAAFETs, with vertically stacked silicon nanowires (NWs), could replace FinFETs at the 5nm node. Vertical GAAFETs with vertical NWs can be extremely scalable, and are predicted to be used beyond 5nm.