High-speed Pipeline Design for HMAC of SHA-256 with Masking Scheme

In order to speed up the HMAC SHA-256 algorithm, this paper proposes a three-stage pipeline hardware implementation of this algorithm. The 3:2 compressor is used to optimize the critical path delay of the hardware. The synthesis verification is performed on Altera's Cyclone II FPGA platform. The throughput rate reaches 875.22Mbps. After that, the simulation of the correlation power analysis (CPA) is carried out to recover the key of the designed HMAC SHA-256 hardware by using 4000 simulated energy traces, which proves the design's shortcomings in resisting the power analysis attack. Therefore, a masking scheme is proposed for this CPA attack, and its FPGA synthesis is also fulfilled. The throughput rate of the masked HMAC SHA-256 algorithm reaches 655.66Mbps, which is 25% lower than the one without masking.