Power Delivery Network Optimization In High Speed BGA Package

As data rates for high speed interconnect systems reach multi-gigahertz data rates, accurate modeling of power delivery network (PDN) at the initial stage of design becomes increasingly challenging. This paper presents a design and analysis for PDN with more focus on BGA package PDN optimization. in such a way that the supply in chip is within its tolerable specifications. A PDN is modelled from die to BGA based on signal specification, power requirement, package size requirement, power bump and cover cell decap information. PDN is analyzed both in terms of SSO noise (time domain) and target impedance (frequency domain). An optimized PDN model is proposed after extensive pre-layout analysis and the same is verified through post layout simulations.