The 2.8mm by 2.6mm sensor is integrated in 130nm CMOS imaging technology and incorporates receiver elements at pitch. Each receiver element contains a single p-well/deep-n-well SPAD biased at 15.2V (1.3V excess bias) with a dead time of 12ns, a median dark count rate of 6kHz at room temperature and a photon detection probability of 37% at 450nm. The mm active area is chosen for ease of alignment to POF or VLC optics but can be adjusted electronically by disabling areas of receiver elements. Figure 29.7.1 shows a simplified schematic of the chip architecture. A receiver element (RE) comprises a SPAD interfaced to a NMOS passive quench, enable SRAM and toggle-flop. The toggling RE output encodes photon events on both rising and falling edges. A row XOR tree combines 32 RE outputs in an asynchronous DDR sequence at a maximal rate of around 900MHz (1.8Gphotons/s) limited only by wiring parasitics (not SPAD dead time). The RE array divides into two sets of 64-row XOR trees feeding digital readout chains placed on the left and right of the active area. Figure 29.7.2 shows the row parallel interface circuit, consisting of three 8b ripple counters, sampling and converting the asynchronous DDR row input signal to a synchronous binary count without dead time. The three counters are operated in a round robin fashion, so that in every sampling clock cycle one counter is reset, one is being read out and one is counting. A local state machine rotates continuously around the counters. The 128 sets of row counters operate in parallel and their outputs are added through a pipelined 7-stage adder tree to give an overall, 16b synchronous sum of SPAD events. The entire digital readout operates from a sample clock generated by an on-chip PLL with programmable frequency up to 800MHz and distributed through clock trees to the pipelined adder. This digital readout replaces the TIA, analog signal conditioning and ADC chain of conventional APD/PD based receivers and will scale favorably to advanced nanometer process nodes. It also lends itself to the integration of the DSP required for complex modulation schemes.
Abstract:
III-nitride laser diodes (LDs) are promising sources for light fidelity (LiFi) networks, underwater wireless optical communications (UWOC), and plastic optical fiber (POF...Show MoreMetadata
Abstract:
III-nitride laser diodes (LDs) are promising sources for light fidelity (LiFi) networks, underwater wireless optical communications (UWOC), and plastic optical fiber (POF) communications [1] due to their high modulation bandwidths (>5GHz) compared to LEDs (<;20MHz). Their narrow linewidths also enable robust free-space Gb/s LiFi links in the presence of high intensities of sunlight through selective spectral filtering. Fully integrated CMOS visible light communications (VLC) receivers have recently been developed to enable miniaturised and low cost Gb/s LD-based links [2]. Sensitivity of these devices is constrained by electrical noise sources such as thermal, shot or excess noise related to the employment of PIN photodiodes (PDs) or linear avalanche photodiodes (APDs) and their amplification circuits. The extremely high gain of SPADs operating in Geiger mode allows quantum sensitivity limits to be approached [3, 4]. A SPAD receiver (RX) for fiber optic applications achieved 200Mb/s at 6.5×10-3 BER within 24dB of the quantum limit [3]. In this paper, we demonstrate a fully integrated CMOS SPAD RX SoC extending this data rate by 2.5× to 500Mb/s, whilst improving sensitivity to -46.1dBm, reducing the margin to the quantum limit to only 15dB. Our RX architecture permits massively parallel (4096) photon event summation to be achieved at a high fill-factor (43%) and sample rate (800MHz). Detector redundancy obviates the requirement on current RX implementations that the SPAD dead time be matched to the symbol period to achieve the maximum data rate [3, 4, 5]. Another advantage is that complex modulation schemes such as OFDM or PAM can be applied for high spectral efficiency and multipath interference mitigation. We demonstrate the RX in a practical, background insensitive VLC link at 1m in 1klx ambient conditions using a 450nm LD. The higher power consumption and dead time pile-up nonlinearity of the SPADs at high signal levels, leads us to conclude that the practical use of this device to be in assistance (rather than replacement) of existing APD or PIN RXs for LiFi, UWOC and POF applications towards extended link range or maintaining a low rate link in highly scattering environments.
Date of Conference: 17-21 February 2019
Date Added to IEEE Xplore: 07 March 2019
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