A Low-Jitter 300MHz CMOS PLL for Double Data Rate Applications

This paper reports on the design of charge pump phase-locked loop (CPDPLL) for internal clock generation purposes in data processing IC. The developed PLL is implemented in 0.25-μm CMOS process and has no external passive components. The synthesizer operates in the range of 3.3V±10% power supply down to 2.7V at a VCO maximum frequency of 300 MHz. Typical VCO operating regime vary from 100 MHz to 300 MHz. Timing jitter parameters are improved and IC double data rate operation without faults is maintained. PLL characteristics are verified when being integrated onto a complex IC layout. The minimum value of peak-to-peak (RMS) cycle-to-cycle jitter is simulated to be 70ps (12ps). The reference frequency is 3.125 MHz, which corresponds to output multiplication factor of 96. The design concepts of the proposed CPDPLL synthesizer are briefly discussed.