Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips

With the development of semiconductor industry and integrated circuits, the performance of processors has been advanced steadily. More and more devices including cores, memories and peripherals are being integrated in chips to meet the requirements of high performance applications. The rapid increase in chip complexity makes it difficult for these devices to work efficiently. In order to facilitate efficient chips systems, we proposed a task scheduling algorithm for Chip Multi-Processors (CMP) which are called Homogeneous Earliest-Finish-Time (HoEFT) algorithm. We use this algorithm to finish two benchmarks on a chip system consisting of eight Processing Elements (PEs) and a 16MB shared memory. The results show that these PEs can reach reasonable utilization under HoEFT algorithm.