Energy Efficient FDSOI and FinFET based Power Gating Circuit Using Data Retention Transistor

Fully Depleted Silicon-on-Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are replacing the bulk MOSFET processes for lower technology nodes. Bulk MOSFETs suffer from severe short channel effects and leakage issues. Sleep transistor based power gating circuits are typically used to address leakage power. In this paper, data retention transistor along with sleep transistor is used to improve the performance. The proposed technique is implemented in 20nm FDSOI and 20nm FinFET technology. Simulations are performed in HSPICE and 2-input NAND gate is used for test purpose. It is observed that FinFET-NAND gate consumes 3.75 times less energy compared to FDSOI-NAND gate during active mode. However, FinFET-NAND gate consumes 1.05 times more energy than FDSOI-NAND gate during hold mode.