Experimental and Numerical Study on Silicon Die Strength and its Impact on Package Reliability

Semiconductor devices become more complicated and the need for the use of semiconductor chips in portable products increases, the need for thinner chips and packages becomes greater. It brings great challenges of processing, handling, and understanding smaller components and, in particular, thinner dies. In the meantime, high reliability remains a critical necessity. The silicon die strength can be adversely affected during various manufacturing processes, such as thinning and dicing. A realistic understanding of the die strength measurement significance is very important for process monitoring and package selection, and risk assessment in the early design stage. The three-point bending test was used to determine the die strength on several samples embedding different Front-End configurations from simple bare silicon up to a real CMOS product with brittle ULK BEOL stack and copper patterning. A 3D anisotropic model based on finite element simulation was developed to assess the relevance and the limitations of the measurement method. SEM analysis were introduced to support the discussion. It has been concluded the highest is the die strength, the smallest should be the sample supporting blade span. However intrinsically to the dicing method and the three-point bending test, the die strength value dispersion is consequently spread.