Study on Electrical Performance and Mechanical Reliability of Antenna in Package (AIP) with Fan-Out Wafer Level Packaging Technology

In this study, antenna in package (AIP) is fabricated based on fan-out wafer level packaging (FO-WLP) technology. Co-design modelling and simulation have been conducted considering electrical performance, wafer process, and solder joint reliability to optimize package structure design and material selection. Electrical simulation results shows that package with 45 ° rotated chip has better electrical performance than package without chip rotation. However, package with 45 ° rotated chip has lower solder joint reliability. Parametric study has been carried out to enhance board level solder joint life under TCOB condition. Process dependent wafer warpage simulation is carried out to identify critical process and reduce wafer warpage through optimizing structure and materials. Through Co-design modelling and simulation, final test vehicle design is finalized and wafer process is successfully conducted.