On the Design of Energy-Efficient I/O Circuits for Interposer-based 2.5D System-in-Package

Interposer-based 2.5D System-in-Package (SiP) allows heterogeneous integration while promising lower cost and higher yield than TSV-based 3D integration [1] [2] [3]. Communications between dies in SiP are similar to those in System-on-Chip (SoC), except SiP is using wires in silicon interposers which have larger linewidth and show inductive properties. The total number of input/output (I/O) circuits to drive on-interposer wires is much larger than off-chip I/Os in SoC. Hence, design of lightweight I/O circuits is critical for 2.5D integrations, and digital singled-ended signaling has emerged as a preferred choice.