Rapid Fabricating sub-50 nm FD-SOI : by Secondary Ion-Cut Processing

One of the things that characterizes the fully depleted silicon-on-insulator (FD-SOI) devices is the ultralow energy consumption. It lets FD-SOI wafers be one of the best candidate materials for manufacturing 5G devices for the Internet of things (IoT), artificial intelligence (AI), and many wireless applications. By using our proposed approach to fabricate FD-SOI wafers employing the ion-cut process, the thickness of the desired as-split silicon can be thinned to 100 nm or less with a pre-deposited Si/SiO
₂
bilayer. Through the nanonization in thickness of the desired as-split layer, the anneal temperature for an efficient layer split (called primary ion cutting) reduced to 400°C from 500°C due to the inside hydrogen concentration in being supersaturated. It is worth noting that annealing at such a low temperature cannot fully annihilate the implant damage at the peak location in where promoting the occurrence of secondary ion-cut processing. After secondary ion cutting and high-temperature annealing in argon, which also causes thermal smoothening, the transferred silicon layer was directly reduced to sub-50 nm without requiring an additional polishing step.