Design a Low voltage & Low power multiplier-free pipelined DCT architecture using hybrid full adder

This paper proposes a new hybrid full adder design along with the comparative analysis of various 1-bit full adder designs. In the proposed design pass transistor based XOR-XNOR design has been used along with an inverter and two multiplexers that can operate at low power, voltages with reduced propagation delay, power delay product (PDP) and total chip area. The proposed design has been compared with various proposed full adder designs with full and non-full swing output voltage for total current withdrawn with change in input voltage along with power consumption, delay and area for 1-bit full addition. The proposed design was schematized by DSCH2 tools and layers are simulated by Microwind tool using 70nm, 90nm, 120nm technology and corresponding voltage of 0.7V, 1V,1.2V. Furthermore, the proposed full adder design has been implemented into a multiplier-free DCT architecture suitable for VLSI design to further enhance it for low voltage, low power and less delay operation.