VLSI SYSTEMS FOR SIMULTANEOUS IN LOGIC SIMULATION

Logic simulation used in conjunction with functional verification verifies the correctness of an integrated circuit. Verification methodologies can be formal or simulation based. Formal based methodologies use exhaustive mathematical techniques to prove circuit responses to all possible inputs and all possible reachable states of the circuit conform to specification. These methods do not rely on the generation of input to verify the design. Simulation based methodologies aims at uncovering design errors by thoroughly exercising the current model of the circuit. The aim of this paper is to present a platform for efficient parallel simulation of high level specification of the system written using RTL/C/C++ language. For the experimental purpose, the Zybo a heterogeneous platform board has been considered in this work. Zybo board is a development kit which provides the designer to develop or test designs. The board contains all the essential interfaces communications and associate functions to enable a wide range of applications. The most significant part on this board is Xilinx Zynq-7000 All Programmable SoC (Zynq SoC) which consists of a dual ARM Cortex-A9 CPU based PS (Processing System) as well as Xilinx hardware PL (Programmable Logic) on the same chip and supports hardware-software co-design.