Physics of hole trapping process in high-k gate stacks: A direct simulation formalism for the whole interface system combining density-functional theory and Marcus theory

Charge trapping defects in high- κ dielectrics and at their interfaces are known to be a challenging obstacle for the silicon based modern transistors. To facilitate the solution of such problems, a deeply physical understanding of the charge trapping process at atomistic scale is mandatory. As such, we propose, for the first time, a direct method to calculate the exact hole trapping rates explicitly in the high- κ gate stack consisting of silicon channel, SiO
₂
interfacial layer and HfO
₂
. The physics of multiple-path (by trap locations) hole trapping processes is revealed by combining density-functional theory and Marcus theory. The roles of physical quantities including defect reorganization, coupling constant and Gibbs free energy are discussed. It is suggested that oxygen vacancies at high- κ interface with interfacial layer SiO
₂
are dominant hole traps under NBTI stress. The developments and findings provide not only a deep physical insight into the hole trapping related reliability degradation mechanism, but also a new simulation framework.