Integrating Graphene into Future Generations of Interconnect Wires

The escalating RC delay and diminishing reliability of Cu interconnect present immense challenges for continued integrated circuits performance improvement. This paper reviews the use of single-layer graphene as the diffusion barrier and capping layer to extend scaling of Cu into future generations of interconnects. With graphene barrier/capping layer, processor core simulations predict an 8% speed boost or 12% energy saving, plus higher tolerance for process variations. Single-layer graphene (3.35 Å thick) provides 3.3× longer barrier lifetime than 2 nm TaN. Barrier reliability is expected to further improve with transfer-free and single-crystalline graphene. In-situ low-temperature grown graphene (<;0.7 nm thick) improves Cu electromigration lifetime by 10× than Cu with 2 nm CoWP. For interconnect scaling beyond Cu, we discuss the potential benefits and challenges of employing multilayer graphene as a Cu replacement. Multi-layer graphene shows better resistivity scaling trend with FeCl
₃
doping and higher immunity to electromigration. Replacing Cu with multilayer graphene, processor cores achieve 9% higher speed or 16% less energy consumption. Spin-on-glass encapsulated multilayer graphene shows two times longer electromigration lifetime than CoWP capped Cu.