Characterization and understanding of slow traps in GeOx-based n-Ge MOS interfaces

The properties of slow electron traps in n-Ge MOS interfaces over a wide range of electrical field across gate oxides (E
_ox
) are systematically investigated. It is found through careful examination of the CV hysteresis that slow trapping under low E
_ox
conditions is attributed only to electron trapping into existing slow traps. Under large E
_ox
conditions, on the other hand, generation of slow electron traps and hole trapping are found to additionally affect the slow trapping characteristics. We propose a new measurement scheme to discriminate existing and generated slow electron traps and apply this method to the three different GeO
_x
-based MOS interfaces in order to clarify the nature of slow traps. It is revealed from this analysis that a pre-plasma oxidation process reduces existing slow electron traps and improves slow trapping in low E
_ox
. On the other hand, ultrathin Y
₂
O
₃
insertion reduces generation of slow electron traps and improves slow trapping in high E
_ox
.