I. Introduction
Today, Si-IGBTs (Insulated Gate Bipolar Transistors) are used as the main stream power switching device [1]–[3], and their improvement is still continued by various ways [4]–[7]. As an attempt to further enhance Si-IGBT performance, a 3D scaling concept was proposed (Fig. 1 and Table 1) [8]. That is, similarly to the CMOS scaling, all the geometrical dimensions, both horizontal and vertical, as well as gate voltage, are scaled down proportionately, while keeping the cell pitch W constant. A major effect of this scaling is the reduction of on-state voltage drop (Vcesat), which is realized by the Injection Enhancement (IE) effect [8], and also lowered trench-gated region resistance. This leads to reduced chip size and cost. Another apparent effect is the reduction of gate voltage. Traditionally, the gate drive voltage has been 15V. However, if this voltage can be reduced to 5V, standard low cost CMOS logic devices with 5V I/O can be used for the gate drivers. This will reduce the driver power by around 1/10. In addition, high integration level of CMOS LSIs will open up new possibilities of smarter digital control [9], enabling more efficient and safer operations of IGBTs. Noise issue could be also solved by digital processing [9].
Scaling principle of trench gate IGBTs.
Structural parameters of scaled IGBTsCell pitch, | 1 | 1 |
Mesa width, S | 1 | 1/3 |
Trench depth, | 1 | 1/3 |
p-base depth, | 1 | 1/3 |
Gate oxide thickness, | 1 | 1/3 |
Gate voltage, | 1 | 1/3 |