On the Performance of FPGA Implementation of Block Matching Algorithms for Video Motion Estimation

FPGA Implementation of pipelined architecture for video motion estimation is achieved and captured using Handel-C within DK4 suite environment. The developed architecture is ported on RC203 prototyping board, featuring a VirtexII XCV3000 FPGA device. Four famous algorithms which are the Full Search Algorithm (FSA), Three Steps Search algorithm (TSSA), Minimum Search Algorithm (MSA) and Diamond Search Algorithm (DSA) are implemented. To evaluate the architecture performances, three criterions are used: the processing speed (Computing Time: CT, measured in ms), image quality (Signal to Noise Ratio: SNR) and required hardware resources (number of occupied slices on the FPGA board). In order to achieve this task, three video sequences widely used in video processing (Akyo sequence, Forman sequence and Flower garden sequence), have been applied. Obtained results show that the computing time is enormously reduced up to 17%for 256x256 pixels/frame and up to 14% for 512x512 pixels/frame in respect to the one of FSA) when using TSSA, MSA and DSA, and this is without a big sacrifice in image quality and resources amount.