Implementation Ring Oscillator Physical Unclonable Function (PUF) in FPGA

This paper is describing the implementation and development of a Physical Unclonable Function (PUF) system for security and authentication. The PUF is tried to be implemented on an FPGA board and compared with similar FPGA board to catch the difference. In this case, the PUF is implemented on Cyclone IV, Intel FPGA board. The chosen FPGA are Cyclone IV EP4CE115F29 as FPGA 1, and Cyclone IV EP4CE10E22C8N as FPGA 2. The type of PUF used is Ring Oscillator (R-O) PUF. The result is shown, for testing the occurrence probability of a value 1 or P(bi=1) for each bit on two FPGA boards. In FPGA 1, the largest value of P(bi=1) is found at the first bit and the smallest value of P(bi=1) is at the fourth bit. For FPGA 2, the largest value of P(bi=1) is at the 13th bit, and the smallest value of P(bi=1) is at the 12th bit. For the average stability value at any position expressed by the Si parameter, the largest Si value on FPGA 1 is at the 4th-bit position and the smallest is at the 11th bit. For FPGA 2, the largest Si value is on the 12th bit while the smallest one is at position 11. In this work, the Hamming distance (HD) of the ROPUF output of both FPGA 1 and 2 are analyzed. For the two FPGA's, the Intra HD results are found to be unsatisfactory because there are still many changes in bit value (bit-flip) are within 1 - 2 bits. On the other hand, the Inter HD values obtained appear to be adequate with the average bit-flip in the range of 3-4 bits. This can be caused by the influence of random environmental conditions, for example, due to the fluctuations of ambient temperature.