Hardware Implementation of a MIMO Channel Emulator for high speed WLAN 802.11ac

In this paper, we present a hardware implementation of a 4×4 MIMO channel emulator for WLAN 802.11ac. High sampling rate and scalable number of taps are targets of MIMO channel emulator. We propose a design of MIMO channel emulator with parallel architecture. We also reduce the number of hardware calculations by using many pre-calculated parameters from software calculations. An implementation on Xilinx Virtex-7 V2000T occupies 929142 slice registers about 38% of the available configurable slice registers and 349416 slice LUTs about 29% FPGA's slice LUTs. The maximum frequency of our emulator is 305.181 MHz, which means it can respond the sampling rate of 802.11ac baseband IQ signal.