Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design

Bundled-data designs can mitigate many of the ill effects of process, voltage, and temperature (PVT) variations. This paper describes an open-source CAD flow to synthesize BD designs from RTL specifications, using perl and TCL scripts that drive commercial tools. The flow called Edge has been developed using experiences from both an open-source CPU called Plasma and a Qualcomm Technologies, Inc. industrial design.