Resistive Open Defect Detection in SoCs by a Test Method Based on Injected Charge Volume after Test Input Application

A test method is proposed of resistive open defects in an SoC by means of charge volume injected from the VDD terminal. The charge is injected after providing a test input vector from a charge injector instead of a DC power voltage source. It is shown by Spice simulation that a resistive open defect in four parallel inverter chain circuits of 30 stages whose resistance is larger than 10k$\Omega$ can be detected by the test method.