Comparison of Braun Multiplier and Wallace Multiplier Techniques in VLSI

In this paper the concept that is used is power efficient multipliers which are very important part of all VLSI system design which provides High speed with low power consumption which are the key requirements for any VLSI design. This paper proposes an efficient implementation of a high speed with low power multiplier using shift and adds methods and this paper presents the implementation of Braun multiplier and Wallace Multiplier using Cadence (Encounter) RTL Complier with simulation which includes creating the Test circuit for each block that is combined together which forms Multiplier. In this paper, Braun Multiplier and Wallace multiplier are simulated by creating the schematic circuit for each of the building blocks such as the AND gate, OR gate, NOT gate, EXOR gate, Half Adder, Full adder and are tested using a test circuit for each of the above blocks. These test circuits are simulated and synthesized using the Cadence tool. Symbol for these building blocks are generated and are called to construct the structure of Braun Multiplier and Wallace Multiplier. Then the multipliers are compared with respect to the number of transistors used which will provide the area occupied and power consumed. Cadence software is used to implement the schematic circuits of each block and all the blocks are simulated using cadence tool and also symbols are created which are assembled together to form a test circuit and all the analysis are tested and also synthesized using Cadence.