Test Methodology & Neutron Characterization of Xilinx 16nm Zynq® UltraScale+™ Multi-Processor System-on-Chip (MPSoC)

This paper presents a test methodology using Xilinx System Validation Tool (SVT) design suite to characterize the single event response of Xilinx's 16nm Zynq Ultrascale+ MPSoC dual & quad ARM core processors. Accelerated SEU beam test of a XCZU9EG device was performed using the 64MeV Proton source at Crocker Nuclear Laboratory (CNL). Single-event characterization results are presented and categorized in terms of detectability and correctability. SEU test results show that the overall Processor System (PS) FIT FIT is ≤ 1, with all safety mechanisms enabled and no uncorrectable events were observed in the PS RAM.

I. Introduction

Multiprocessor Systems-on-Chip (MPSoC) devices are becoming a prevalent category of very-large-scale integrated (VLSI) systems. These use multiple programmable processors as system components to achieve tight time-to-market design goals, maximize design reuse, simplify the verification process and provide flexibility and programmability for post-fabrication reuse of complex platforms [[1], [2]]. MPSoCs are widely used in networking, automotive, communications, signal processing, and multimedia among other applications [1]. However, they have been proven to be vulnerable to errors created in radiation environments. It is crucial to understand how single event effects (SEE) affect the functionality of an MPSoC and to properly classify the errors for safety applications as well as to minimize system-downtime.