Folding and Register Minimization Transformation on DSP Filter

This paper presents folding transformation technique on a second order IIR filter or Biquad filter and third order IIR filter. Retiming is done prior to folding transformation. The advantages of folding are reduction in number of arithmetic circuits such as adders and multipliers, time multiplexing of numerous algorithms onto a single arithmetic circuit resulting in low silicon area for integrated circuits and can be processed on single or multiple clocks. As the number of arithmetic circuits decrease, the number of registers increases, so register minimization technique is used. This technique enables to reduce the area required by memory along with the reduction in the number of memory units. The algorithm is coded in VHDL and implemented on Xilinx Virtex7 XC7VX330T. On comparing the device utilization of the following pairs of circuits, the percentage improvement of folded DFG over filter DFG is nearly 35%, register minimized folded DFG over filter DFG is nearly 23% and register minimized folded DFG over folded DFG is nearly 16%.