A New Multilevel Inverter Topology with Reduced Switch Count and Device Stress

Multilevel Inverters (MLI) are becoming more and more popular in the medium and high voltage grid power applications. This is due to several inherent advantages of MLI over two-level inverters such as high-quality output, lower device ratings, and several others. In this paper, a new cascaded MLI topology is proposed. The proposed topology not only reduces the number of isolated DC voltage sources, IGBTs and Diodes but also keeps the voltage stress, which is an imperative factor in influencing the cost of the inverter, across each switching device to a low and constant value with the increase in number of levels of the inverter. The proposed topology has also got redundant switching states which are useful for keeping equal power balance among the cells. The validation of the proposed MLI is substantiated with both computer simulations using MATLAB/SIMULINK software and by developing the laboratory prototype for a 7-level inverter.