I. Introduction
In modern day design methodologies, many applications, including wireless sensor networks, microprocessor and microcontroller chips, memory cells, etc. require ultralow-power circuits [1], [2]. Scaling of the MOS transistors is an effective process to reduce power dissipation [3]–[7], but it results in increase of the leakage currents. These surging leakage currents also have an adverse effect on operation of MOS based SRAM cells [8], [9]. A conventional 6T SRAM cell operation at low supply voltages results in degradation of performance parameters viz. delay, data retention stability, write and read stabilities [10]–[12]. Some of the alternatives of the MOS transistors can be, use of Fin-FET based devices, 3D designs, Nano-computing, etc. These technologies help to enhance the performance parameters at low supply voltages, but this area of research is very expensive and requires huge investments [13], [14]. Therefore, focus is mainly on traditional CMOS based design technologies that can also address performance issues at low supply voltages [15]–[17].