Comparison of Two All-Digital Frequency Synthesizers with a Jitter Removal Circuit

Digital frequency synthesizers are key components in wireless communication systems. Their single-bit output can be achieved by a Sigma Delta Modulator (SDM) which improves the noise shaping characteristics as well as the performance in terms of Signal-to-Noise-and-Distortion Ratio (SNDR). However, hardware implementation in FPGAs limits their overall performance due to undesired jitter effect introduced by the FPGA, which is translated into phase noise. In this work we present the hardware implementation of two all-digital frequency synthesizers based on SDMs which are afterwards corrected by a laboratory circuit for suppressing the jitter effect introduced by the clock reference of the FPGA. Comparison of the Quadrature Homodyne Filter (QHF) and Multiplier-Free QHF (MFQHF) SDM architectures in terms of digital synthesis results, SNDR, sampling rate and jitter-free spectrums are provided to demonstrate their capabilities in order to consider them as viable choice for digital frequency synthesis.