A 14-bit 500MS/s and 1GS/s Configurable Pipelined ADC with Background Calibration

A 14-bit 500-MS/s and 1-GS/s configurable pipelined Analog-to-Digital Converter (ADC) is implemented in 28 nm CMOS. The ADC leverages dither and correlation-based background digital calibration techniques to correct the interstage gain and settling errors. A dithering technique is employed to inject a large dither signal to randomize residual non-linearity in the pipelined ADC. In order to speed up the correlation-based calibration, a variable-step-size LMS algorithm is used to extract the error coefficients. An optional interleaved mode is provided, where the two ADCs on a chip are time-interleaved to realize a single 14-bit 1 GS/s ADC. After calibration, the ADC achieves a 61.64 dB SNDR and 71.83 dB SFDR at 1 GS/s sample rate. The chip occupies 6 mm
²
area and consumes 1.4 W at 2.0/1.0 V supplies.